1. Field of the Invention
The present invention relates generally to the manufacture of microelectronic devices. In particular, the present invention relates to a method of thinning a wafer-to-wafer vertical stack, which prevents edge chipping and/or cracking.
2. State of the Art
Greater packaging density of microelectronic devices is an ongoing goal of the computer industry. One method of increasing the density of microelectronic devices is to stack the individual microelectronic dice within these devices. One method of fabricating a stacked microelectronic device is to fabricate integrated circuitry on active surfaces of individual microelectronic wafers, stack them, then dice the stacked wafers into individual stacked microelectronic devices. FIG. 13 illustrates a first microelectronic wafer 202 having an active surface 204 and an opposing back surface 206. The active surface 204 includes integrated circuitry (illustrated generically as an integrated circuitry layer 208 within the illustrated dash lines) which is formed in the first microelectronic wafer 202 less than about 10 microns deep into the first microelectronic wafer 202. This integrated circuitry layer 208 is the functional area of the first microelectronic wafer 202. As will be understood by those skilled in the art, the microelectronic wafer 202 may be about 700 to 800 microns thick.
As shown in FIG. 14, an interconnect layer 212 is formed on the first microelectronic wafer active surface 206. The interconnect layer 212 may comprise multiple layers of conductive traces (not shown) separated by dielectric material layers (not shown). The first microelectronic wafer interconnect layer 212 provides routes for electrical communication between integrated circuit components within the integrated circuits and between integrated circuit components and external devices (not shown). As further shown in FIG. 14, the structure includes an exclusion zone 238 around the outer edge 210 of the first microelectronic wafer 202. The exclusion zone 238, usually between about 2 and 3 mm width, is necessary for uniform current distribution into a seed layer (not shown) for electroplating processes during the fabrication. Thus, any material used in during fabrication (e.g., photoresist, etc.), which falls within the exclusion zone 238 is removed (e.g., edge bead removal processes, etc.).
As shown in FIG. 15, a second microelectronic wafer 216 is provided, which also has an active surface 218, an integrated circuitry layer 222, and an interconnect layer 224 disposed thereon. The first microelectronic wafer interconnect layer 212 is aligned with the second microelectronic wafer interconnect layer 224 and attached using an electrically isolated metal bonding technique, as will be understood by those skilled in the art. The attachment of the first microelectronic wafer interconnect layer 212 and the second microelectronic wafer interconnect layer 224 may electrically interconnect the first microelectronic wafer integrated circuitry layer 208 and the second microelectronic wafer integrated circuitry layer 222.
Although the 700 to 800 micron thickness of the first microelectronic wafer 202 is required for the fabrication of the first microelectronic wafer integrated circuit layer 208, only the first microelectronic wafer integrated circuitry layer 208 is functional (it is, of course, understood that the second microelectronic wafer integrated circuitry layer 216 is also functional). Thus, after the fabrication of the first microelectronic wafer integrated circuit layer 208 and the first micro-electronic wafer interconnection layer 212, a substantial amount of the first microelectronic wafer 202 may be removed (i.e., “thinned”) without affecting the first microelectronic wafer integrated circuitry layer 208. Thinning a micro-electronic wafer makes it possible to route input-output signals, power, and ground to and from the integrated circuitry layer to the back surface of the microelectronic wafer, as will be discussed.
As shown in FIG. 16, the first microelectronic wafer 202 is thinned to a thickness of between about 10 and 100 microns forming a thinned back surface 226. A plurality of conductive vias 228 are formed to extend from the first microelectronic wafer thinned back surface 226 to the first microelectronic wafer integrated circuitry layer 208 to make electrical connections therewith, as shown in FIG. 17. A plurality of interconnect devices 232, such as solder balls, are then attached to the plurality of conductive vias 228 at the first microelectronic wafer thinned back surface 226, as shown in FIG. 18, to form a stacked wafer structure 234. The stacked wafer structure 234 may then be diced or singular, such as with a wafer saw or a laser (not shown) to form discrete packages 236, as shown in FIG. 19.
As previously discussed, the first and second microelectronic wafers 202, 216 each include exclusion zones 238 and 240, respectively, resulting in a portion 250 of the first microelectronic wafer 202 being unsupported. Thus, when the first microelectronic wafer 202 is thinned, the unsupported portion 250 is susceptible to chipping and cracking. As shown in FIG. 20, if the unsupported portion 250 (see FIGS. 16 and 17) chips off during thinning, a chip 242 can extend into the integrated circuitry layer 208, which can damage or destroy the functionality thereof. As shown in FIG. 21, if the unsupported portion 250 (see FIGS. 16 and 17) flexes during thinning, cracks 244 can propagate and extend into the integrated circuitry layer 208 also damaging or destroying the functionality thereof. Furthermore, chips and cracks may also facilitate contaminant incursion during subsequent processing, which may also damage or destroy the functionality of the integrated circuitry layer 208.
Therefore, it would be advantageous to develop methods for fabricating stacked microelectronic device, which reduces or substantially chipping and/or cracking of the microelectronic wafers during a thinning process.